如果您剛剛開始瞭解多核cpu、快取、快取一致性和記憶體的工作原理，那麼一開始可能會有點困惑。有鑑於此，今天的超級使用者問答帖子回答了一位好奇的讀者的問題。

今天的問答環節是由SuperUser提供的，SuperUser是Stack Exchange的一個分支，是一個由社群驅動的問答網站分組。

問題

超級使用者閱讀器CarmeloS想知道CPU的快取何時被重新整理回主記憶體：

If I have a CPU with two cores and each core has its own L1 cache, is it possible that Core1 and Core2 both cache the same part of memory at the same time? If it is possible, what will the value of main memory be if both Core1 and Core2 have edited their values in cache?

CPU的快取記憶體何時被重新整理回主存？

答案

超級使用者貢獻者davidschwartz、sleske和Kimberly W為我們提供了答案。首先，大衛·施瓦茨：

If I have a CPU with two cores and each core has its own L1 cache, is it possible that Core1 and Core2 both cache the same part of memory at the same time?

Yes, performance would be terrible if this was not the case. C***ider two threads running the same code. You want that code in both L1 caches.

If it is possible, what will the value of main memory be if both Core1 and Core2 have edited their values in cache?

The old value will be in main memory, which will not matter since neither core will read it. Before ejecting a modified value from cache, it must be written to memory. Typically, some variant of the MESI protocol is used. In the traditional implementation of MESI, if a value is modified in one cache, it cannot be present at all in any other cache at that same level.

接著是斯萊斯克的回答：

Yes, having two caches cache the same memory region can happen and is actually a problem that occurs a lot in practice. There are various soluti***, for example:

• The two caches can communicate to make sure they do not disagree
• You can have some sort of supervisor which monitors all caches and updates them accordingly
• Each processor monitors the memory areas that it has cached, and when it detects a write, it throws out its (now invalid) cache

The problem is called cache coherency and the Wikipedia article on the topic has a nice overview of the problem and possible soluti***.

金伯利W的最終答案是：

To answer the question in your post’s title, it depends on what the caching protocol is. If it is write-back, the cache will only be flushed back to main memory when the cache controller has no choice but to put a new cache block in already occupied space. The block that previously occupied the space is removed and its value is written back to main memory.

The other protocol is write-through. In that case, anytime the cache block is written on level n, the corresponding block on level n+1 is updated. It is similar in concept to filling out a form with carbon paper underneath; whatever you write on top is copied on the sheet below. This is slower because it obviously involves more writing operati***, but the values between caches are more c***istent. In the write-back scheme, only the highest level cache would have the most up-to-date value for a particular memory block.

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