如果您刚刚开始了解多核cpu、缓存、缓存一致性和内存的工作原理，那么一开始可能会有点困惑。有鉴于此，今天的超级用户问答帖子回答了一位好奇的读者的问题。

今天的问答环节是由SuperUser提供的，SuperUser是Stack Exchange的一个分支，是一个由社区驱动的问答网站分组。

问题

超级用户阅读器CarmeloS想知道CPU的缓存何时被刷新回主内存：

If I have a CPU with two cores and each core has its own L1 cache, is it possible that Core1 and Core2 both cache the same part of memory at the same time? If it is possible, what will the value of main memory be if both Core1 and Core2 have edited their values in cache?

CPU的高速缓存何时被刷新回主存？

答案

超级用户贡献者davidschwartz、sleske和Kimberly W为我们提供了答案。首先，大卫·施瓦茨：

If I have a CPU with two cores and each core has its own L1 cache, is it possible that Core1 and Core2 both cache the same part of memory at the same time?

Yes, performance would be terrible if this was not the case. C***ider two threads running the same code. You want that code in both L1 caches.

If it is possible, what will the value of main memory be if both Core1 and Core2 have edited their values in cache?

The old value will be in main memory, which will not matter since neither core will read it. Before ejecting a modified value from cache, it must be written to memory. Typically, some variant of the MESI protocol is used. In the traditional implementation of MESI, if a value is modified in one cache, it cannot be present at all in any other cache at that same level.

接着是斯莱斯克的回答：

Yes, having two caches cache the same memory region can happen and is actually a problem that occurs a lot in practice. There are various soluti***, for example:

• The two caches can communicate to make sure they do not disagree
• You can have some sort of supervisor which monitors all caches and updates them accordingly
• Each processor monitors the memory areas that it has cached, and when it detects a write, it throws out its (now invalid) cache

The problem is called cache coherency and the Wikipedia article on the topic has a nice overview of the problem and possible soluti***.

金伯利W的最终答案是：

To answer the question in your post’s title, it depends on what the caching protocol is. If it is write-back, the cache will only be flushed back to main memory when the cache controller has no choice but to put a new cache block in already occupied space. The block that previously occupied the space is removed and its value is written back to main memory.

The other protocol is write-through. In that case, anytime the cache block is written on level n, the corresponding block on level n+1 is updated. It is similar in concept to filling out a form with carbon paper underneath; whatever you write on top is copied on the sheet below. This is slower because it obviously involves more writing operati***, but the values between caches are more c***istent. In the write-back scheme, only the highest level cache would have the most up-to-date value for a particular memory block.

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